Variations in Cache Behavior

Reduction in Cache Memory Power Consumption based on Replacement Quantity

Today power consumption is considered to be one of the important issues. Therefore, its reduction plays a considerable role in developing systems. Previous studies have shown that approximately 50% of total power consumption is used in cache memories. There is a direct relationship between power consumption and replacement quantity made in cache. The less the number of replacements is, the less...

Reduction in Cache Memory Power Consumption based on Replacement Quantity

Today power consumption is considered to be one of the important issues. Therefore, its reduction plays a considerable role in developing systems. Previous studies have shown that approximately 50% of total power consumption is used in cache memories. There is a direct relationship between power consumption and replacement quantity made in cache. The less the number of replacements is, the less...

26.5 PVT-Aware Leakage Reduction for On-Die Caches with Improved Read Stability

Leakage control during circuit operation is more challenging than standby mode control due to the short time to deactivate blocks, large overhead energy and run-time leakage variations. This paper proposes circuit techniques that address these challenges to reduce run-time leakage in on-die SRAM caches. A source-biased gated-ground SRAM is proposed; an efficient way to utilize this technique un...

Increasing the Predictability of Modern COTS Hardware through Cache-Aware OS-Design

Real-time operating systems have been around for some time, but they are never designed for being used on modern multi-core processors with unpredictable timing behavior. An important source of unpredictability is the different timing between the processor and the DRAM-controller. Operatingsystem-based cache management is one possibility to reduce the timing variations of the processor by contr...

i2WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations

Modern computers require large on-chip caches, but the scalability of traditional SRAM and eDRAM caches is constrained by leakage and cell density. Emerging nonvolatile memory (NVM) is a promising alternative to build large on-chip caches. However, limited write endurance is a common problem for non-volatile memory technologies. In addition, today’s cache management might result in unbalanced w...

A Power Aware Cache and Register File Design Space Exploration